Co-Designing TinyML Accelerators on FPGAs via Approximate Matrix Decomposition

Hernandez Morales JJ, Mentzos G, Hannig F, Balaskas K, Zervakis G, Henkel J, Teich J (2027)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2027

Publisher: ACM

Conference Proceedings Title: Proceedings of the 32nd Asia and South Pacific Design Automation Conference (ASP-DAC)

Event location: Tokyo JP

ISBN: 979-8-4007-2923-2

DOI: 10.1145/3840404.3860926

Authors with CRIS profile

Jose Juan Hernandez Morales Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Neural Approximate Accelerator Architecture Optimization for DNN Inference on Lightweight FPGAs (NA³Os) May 1, 2024 - April 30, 2027

Involved external institutions

Karlsruhe Institute of Technology (KIT) DE Germany (DE) National Technical University of Athens / Εθνικό Μετσόβιο Πολυτεχνείο GR Greece (GR)

How to cite

APA:

Hernandez Morales, J.J., Mentzos, G., Hannig, F., Balaskas, K., Zervakis, G., Henkel, J., & Teich, J. (2027). Co-Designing TinyML Accelerators on FPGAs via Approximate Matrix Decomposition. In Proceedings of the 32nd Asia and South Pacific Design Automation Conference (ASP-DAC). Tokyo, JP: ACM.

MLA:

Hernandez Morales, Jose Juan, et al. "Co-Designing TinyML Accelerators on FPGAs via Approximate Matrix Decomposition." Proceedings of the 32nd Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo ACM, 2027.

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